1. Field
Exemplary embodiments of the present invention relate to a fabrication technology of a semiconductor device, and more particularly, to a semiconductor device having a buried gate and a method for fabricating the same.
2. Description of the Related Art
As a semiconductor fabrication process is performed in a minute scale, it is difficult to maintain and achieve various element characteristics and processes. Particularly, in 40 nm or less, there is a limitation in forming a gate structure, a bit line structure, a contact structure and the like. Even if the structure is formed, it is difficult to ensure desired device characteristics. In this regards, recently, there has been introduced a buried gate (BG) formed by burying a gate in a substrate. Since an entire gate structure is buried in the substrate, it is possible to easily ensure channel length and width, and to reduce parasitic capacitance which is generated between a gate and a bit line as compared with a planar gate or a recess gate.
Meanwhile, in a semiconductor device having a cell region and a peripheral circuit region, since a buried gate is formed in the cell region, a stepped portion is generated between the cell region and the peripheral circuit region by a height of a peri-gate formed in the peripheral circuit region. To effectively utilize such a stepped portion, a gate bit line (GBL) process of simultaneously forming the peri-gate of the peripheral circuit region and a bit line of the cell region has been introduced.
However, in the GBL process according to the conventional art, since the bit line of the cell region and the peri-gate of the peripheral circuit region are simultaneously formed, a bit line having a large height corresponding to the height of the peri-gate is formed, resulting in an increase in parasitic capacitance between bit lines in the cell region. Therefore, a bit line sensing margin is reduced.